DESCRIPTION DU 68HC811E2
Structure interne
Registres internes
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ADCTL ADR1 ADR2 ADR3 ADR4 BAUD BPROT CFORC CONFIG COPRST DDRC DDRD HPRIO INIT OC1D OC1M OPTION PACNT PACTL PIOC PORT A PORT B PORT C PORTCL PORTD PORTE PPROG SCCR1 SCCR2 SCDR SCSR SPCR SPDR SPSR TCNT TCTL 1 TCTL 2 TEST1 TFLG1 TFLG2 TMSK1 TMSK2 TIC 1 TIC 2 TIC 3 TOC 1 TOC 2 TOC 3 TOC 4 TI4O5 |
$1030
$1031 $1032 $1033 $1034 $102B $1035 $100B $103F $103A $1007 $1009 $103C $103D $100D $100C $1039 $1027 $1026 $1002 $1000 $1004 $1003 $1005 $1008 $100A $103B $102C $102D $102F $102E $1028 $102A $1029 $100E $1020 $1021 $103E $1023 $1025 $1022 $1024 $1010 $1012 $1014 $1016 $1018 $101A $101C $101E |
A/D Control Register A/D Result Register 1 A/D Result Register 2 A/D Result Register 3 A/D Result Register 4 SCI Baud Rate Register EEPROM Block Protect Register Compare Force Register COP, ROM, and EEPROM Enables Arm/Reset COP Timer Circuit Data Direction for Port C Data Direction for Port D Highest Priority I-Bit int. and Misc. RAM and 1/0 mapping Reg. 0Cl Action Data Register OCl Action Mask Register System Configuration Options Pulse Accum. Count Register Pulse Accum. Control Register Parallel I/0 Control Register I/0 Port A 0utput Port B I/0 Port C Altenate Latched Port C I/O Port D Input Port E EEPROM Prog. Control Reg SCI Control Register 1 SCI Control Register 2 SCI Datal Register SCI Status Register SPI Control Register SPI 0ata Register i SPI Status Register Timer Counter Register Timer Control Register in Timer Control Register in Factory Control Register : Timer Interrupt Flag 1 Timer Interrupt Flag 2 Timer Interrupt Mask 1 Timer Interrupt Mask 2 Input Capture 1 Register Input Capture 2 Register Input Capture 2 Register 0utput Compare 1 Register 0utput Compare 2 Register 0utput Compare 3 Register 0utput Compare 4 Register 0utput Compare 5 Register/Input Capture 4 Register |
Differentes vues du HC11
Vu de dessus sans support
Vu de dessus (empreinte du support)
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Vu de dessous (empreinte du support)
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Giampiero D'AQUINO
Enseignant en Genie Electronique -